Senior Design Verification Engineer (BB-F96AE)
Found in: Neuvoo IL
In this role, you will work closely with the design team to ensure timely delivery of quality designs and be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage.
Education & Experience
B.Sc. / M.Sc. Electrical Engineering / Computer Engineering / Computer Science
calendar_today2 days ago