Design Verification Engineer (BB-37B81)

Found in: Neuvoo IL


Minimum Qualifications
- Leadership capabilities
- 3+ years experience as DV engineer.
- Eager to succeed.
- Accountable & responsible.
- Team player.
- Great communication skills.

Preferred Qualifications
- System Verilog, UVM
- Coverage-driven verification.
- Power aware simulation.
- Gate level simulations.
- Co-sim with Matlab/SysC.
- ASIC familiar with various design blocks including processors/ micro controllers/ hw accelerators.
- System a vast full system understanding.
- Leadership capabilities - MUST.
Leadership experience - Advantage

calendar_today2 days ago


location_on Center District, Israel

work Ethosia

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