Design Verification Engineer (BB-37B81)
Found in: Neuvoo IL
- Leadership capabilities
- 3+ years experience as DV engineer.
- Eager to succeed.
- Accountable & responsible.
- Team player.
- Great communication skills.
- System Verilog, UVM
- Coverage-driven verification.
- Power aware simulation.
- Gate level simulations.
- Co-sim with Matlab/SysC.
- ASIC familiar with various design blocks including processors/ micro controllers/ hw accelerators.
- System a vast full system understanding.
- Leadership capabilities - MUST.
Leadership experience - Advantage
calendar_today2 days ago