IP Design Verification Engineer (BB-51FD4)

Found in: Neuvoo IL


Key Qualifications

  • 3+ years’ experience in digital logic design verification
  • Basic knowledge of SystemVerilog and UVM
  • Experience developing UVM based IP test-benches
  • Experience with complex designs and advanced debug skills ability
  • Experience with verification tools such as simulators, waveform viewers, build/run automation, coverage collection and analysis, gate level simulations
  • Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
  • Ability to work well in a team and be productive under tight schedules
  • Excellent knowledge of one of the scripting languages: Python, Perl, TCL
  • Experience with serial/parallel protocols such as PCIe or DRAM
  • Proven knowledge of formal verification methodology
  • In lieu of UVM knowledge, C/C++ experienced level knowledge
  • Experience with Lab hands-on debug
  • Description In this role, you will be responsible for ensuring bug-free first silicon for part of the IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage. Education & Experience BSc or MSC in Electrical Engineering

    calendar_today2 days ago


    location_on Haifa, Israel

    work Apple

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